1. Field of the Invention
The present invention relates to a circuit for generating a reference current, a circuit for generating a bias voltage and a bias circuit having the reference current generating circuit and the bias voltage generating circuit. More particularly, the present invention relates to a reference current generating circuit capable of generating a reference current constantly at a low voltage, and an amplifier bias circuit capable of providing an operational amplifier with a constant bias voltage based on the reference current.
2. Description of the Related Art
An operational amplifier (hereinafter referred to as an “op-amp”) is widely used in various analog circuits for analog operations or analog amplifications. Analog circuits, which have been used in mobile devices, need to be configured to save electricity and cost in manufacturing process and operation. Recently, op-amps tend to be designed to operate at a low voltage, as low as 1.2V, to be implemented in mobile devices. However, conventional bias circuits for op-amps still require 3V as a power supply voltage due to performance deterioration when operated at 1.2V.
Korean Patent Laid-Open Publication No. 1999-0029934 discloses a reference current circuit that purports to be capable of generating a constant current regardless of variation in power supply voltages and ambient temperature. The reference current circuit includes a first unit to generate a current in inverse proportion to the temperature variation, and a second unit to generate a current in proportion to the temperature variation so as to generate a regulated current. However, the first unit of the reference current circuit has a circuit configuration that makes the circuit difficult to operate properly at a low power supply voltage. If a circuit is made with a smaller dimension, the above reference current circuit may be operated at a low power supply voltage, but technologies for finer processes would be required.
Typically, because resistances of circuit elements increase in proportion to ambient temperature, it is desirable to compensate effects from the increased resistances by increasing the reference current accordingly for stability of the whole device. Therefore, in many cases, only the above second unit is used for generating a reference current, without using the first unit.
FIG. 1 is a circuit diagram illustrating a conventional reference current generating circuit 100. Referring to FIG. 1, the reference current generating circuit generates a current in proportion to temperature variation.
The reference current generating circuit includes a current generating unit 11 with a positive temperature coefficient, a start-up unit 12 and a current output unit 13. The reference current generating circuit has a current property, which functions independently from a power supply voltage VDD when operating at an ordinary range of the power supply voltage, i.e., 2.5V˜3.3V. An output current IOUT may be represented by:
                                          I            OUT                    =                                                    2                ×                                  L                                      MP                    ⁢                                                                                  ⁢                    2                                                                                                R                  2                                ⁢                                  μ                  p                                ⁢                                  C                  OX                                ⁢                                  W                                      MP                    ⁢                                                                                  ⁢                    2                                                                        ⁢                                          (                                  1                  -                                      1                    /                                          A                                                                      )                            2                                      ,                            Equation        ⁢                                  ⁢                  (          1          )                    where
      A    =          (                                    L                          MP              ⁢                                                          ⁢              1                                            W                          MP              ⁢                                                          ⁢              1                                      /                              L                          MP              ⁢                                                          ⁢              2                                            W                          MP              ⁢                                                          ⁢              2                                          )        ,L denotes a length of a gate of a MOS transistor, W denotes a width of the gate of the MOS transistor, μp denotes a mobility of an electric hole, and COX denotes a capacitance of a gate oxide per unit area.
FIG. 2 is a schematic diagram illustrating a conventional operational amplifier 200. Particularly, a circuit in FIG. 2 is a folded-cascode op-amp, the most popular type of op-amps fabricated by the CMOS technologies, having a common-mode feedback (CMFB) circuit. Referring to FIG. 2, the folded-cascode op-amp includes a differential amplifier 21 having differential inputs and outputs, and a biasing unit 22 for biasing the differential outputs.
The biasing unit 22 and the CMFB respectively require first through fifth, bias voltages VBS1, VBS2, VBS3, VBS4 and VBS5. Thus the folded-cascode op-amp still needs an additional circuit to constantly provide such bias voltages. Particularly, a voltage difference between the first and third bias voltages VBS1 and VBS3, a voltage difference between the second and third bias voltages VBS2 and VBS3, and a voltage difference between the fourth and fifth bias voltages VBS4 and VBS5 are important for the operations of the biasing unit 22 and the CMFB. Such voltage differences need to be maintained constant, otherwise, the op-amp may not properly operate with a low power supply voltage.
FIG. 3 is a circuit diagram illustrating a bias voltage generating circuit 300 for the conventional operational amplifier in FIG. 2. Referring to FIG. 3, the bias voltage generating circuit may be generally viewed as six current mirrors, mirroring currents with respect to a seventh PMOS transistor MP7.
A reference current IOUT flows through the seventh PMOS transistor MP7 from a reference current generating circuit (not shown). The first to third PMOS transistors MP1 to MP3 respectively form current mirrors with the seventh PMOS transistor MP7, and currents flow through the first to third PMOS transistors MP1 to MP3 according to a size ratio of each PMOS transistor. These currents respectively flow through first to third diode-connected NMOS transistors MN1, MN2 and MN3, so that the bias voltage VBS1, VBS2 and VBS3 are generated according to respective equivalent impedances of the first to third NMOS transistors MN1 to MN3. A sixth PMOS transistor and a sixth NMOS transistor are operated as buffers to change levels of bias voltages to be generated. Fourth and fifth NMOS transistors MN4 and MN5 respectively mirror a current flowing through the sixth NMOS transistor MN6. These mirrored currents respectively flow to the fourth and fifth PMOS transistors MP4 and MP5, so that the bias voltages VBS4 and VBS5 are generated according to respective equivalent impedances of the fourth and fifth PMOS transistors MP4 and MP5.
In the bias voltage generating circuit, the bias voltages are dependent on the equivalent output impedances of the transistors MP1 MP2, MN3, MN4 and MN5 that are operated as loads. The output impedances, which are presented by the channel length modulation, may be adjusted by changing size of gates in the MOS transistors. When the bias voltage generating circuit in FIG. 2 is operated with power supply voltages within a usual range, i.e., 2.5V˜3.3V, the output impedance may be maintained steady regardless of variation of the power supply voltage, and the bias voltages may also be maintained steady.
When the bias voltage generating circuit in FIG. 2 is operated within a low range of power supply voltage, i.e., 1.0V˜1.2V, not only the reference current, but also the output impedances may become dependent on the level of the power supply voltage. Thus, the bias voltages are not well maintained and the operation of the op-amp is badly affected.
Additionally, because it is hard to precisely control the output impedances of the load transistors by the CMOS technologies, the bias voltages may not be generated as designed.